Design and Development of VLSI Circuits using Mentor Graphics Tools

Resource Person:

Mr.K.Pradeep,Sr.Application Engineer in Apply Volt

Outcome:

Participants can design and develop digital circuits using Mentor graphics HEP1 tools

Theory Session on “Basics of ASIC Design and ASIC Vs FPGAs,Full Custom Flow and Semi Custom Design Flow, Latest Advancements in VLSI industry” and lab session on “pyxis schematic and ELDO Simulator”.

Lab Session on “RTL to GDS Flow” which includes reading Verilog Netlist in pyxis Layout, Floor –planning placement & Routing(PR),Physical Verification with Calibre(DRC,LVS,PEX).

15^th December 2020:

Lab Session on “Cell Based Design” which includes Floor –planning placement & Routing(PR),Physical Verification using industry standard Calibre tool (DRC,LVS,PEX).

Layout creation from schematic and analyzed parameters like power dissipation,delay etc.,. then there was a demonstration session on process of post layout simulation , RC extraction(XRC) and physical verification step using calibration tool(LVS).