In order to strength the faculty in embedded system domain several programmes were initiated by the Department of ECE. In this regard a two-day training programme was organized during 6-7 December 2018. Thirty six faculty members and Eight M.Tech (Embeded Systems) students were participated in this programme.
Mr.B.Nagendra, was briefly explain the ‘Basics of ASIC Design and ASIC Vs FPGAs, Full Custom Flow and Semi Custom Design Flow, Latest Advancements in VLSI Industry’ in the theory session which was followed by a lab session on ‘Semi Custom Design Flow(HEP-2)’ which includes Design Entity(Verilog): Functional Verification with Questa, Synthesis using Precision/Leonardo: Analyzing Gate-level netlst RTL, Technology Schematic and Critical Path.
The lab session on ‘RTL to GDS Flow which includes Verilog Netlist in PYxis Layout, Floor-Planning Placement &Routing (PR), Physical Verification with Calibre’ was held on afternoon session.
The second day was started with a lab session on ‘Tessent DFT Flow’ which includes the importance of Tessent DFT Tool, Scan Insertion,Silicon test, ATPG and Analyzing reports, which was followed by a lab sessin on ‘Cell Based Design’ in the last session.